Course level

Undergraduate

Faculty

Engineering, Architecture & Information Technology

School

Elec Engineering, Comp Science

Units

2

Duration

One Semester

Attendance mode

In Person

Class hours

Lecture 2 Hours/ Week
Practical 2 Hours/ Week
Applied Class 1 Hour/ Week

Incompatible

CSSE2000 or CSSE3000 or CSSE7011 or CSSE7410

Prerequisite

CSSE1000 or CSSE2010

Recommended prerequisite

Assessment methods

Practicals, project, research assignment, final exam

Course enquiries

CSSE4010@eecs.uq.edu.au

Study Abroad

This course is pre-approved for Study Abroad and Exchange students.

Current course offerings

Course offerings Location Mode Course Profile
Semester 2, 2025 (28/07/2025 - 22/11/2025) St Lucia In Person Profile unavailable

Please Note: Course profiles marked as not available may still be in development.

Course description

CSSE4010 introduces students to the concepts, design methods and state of the art tools for digital system design. The course covers basic digital logic design concepts including logic simplification, combinational and sequential building blocks, arithmetic circuits, finite state machines, and datapath/controller design for custom digital architectures. The course will provide implementation details from a reconfigurable logic perspective and discuss topics related to timing aspects. Students are introduced to hardware description language (HDL) based system design for field programmable gate array (FPGA) based platforms using VHDL as the standard language (other commonly used languages include Verilog, System-Verilog, and different variants of C). Following the conventional HDL based design flow using Xilinx/AMD EDA tools, students will be subsequently introduced to topics such as high-level synthesis, model-based system design and rapid prototyping for FPGAs with alternative tool flows such as Matlab HDL coder. As a compelling application for exploiting hardware parallelism offered by FPGAs, specific design techniques for real-time implementation of digital signal processing (DSP) algorithms with hardwear acceleration on FPGAs will be introduced. 

Archived offerings

Course offerings Location Mode Course Profile
Semester 2, 2024 (22/07/2024 - 18/11/2024) St Lucia In Person Course Profile
Semester 2, 2023 (24/07/2023 - 18/11/2023) St Lucia In Person Course Profile
Semester 2, 2022 (25/07/2022 - 19/11/2022) St Lucia Internal Course Profile
Semester 2, 2022 (25/07/2022 - 19/11/2022) External External Course Profile
Semester 2, 2021 (26/07/2021 - 20/11/2021) St Lucia Internal Course Profile
Semester 2, 2021 (26/07/2021 - 20/11/2021) External External Course Profile
Semester 2, 2020 (03/08/2020 - 21/11/2020) St Lucia Flexible Delivery Course Profile
Semester 2, 2020 (03/08/2020 - 21/11/2020) External External Course Profile
Semester 2, 2019 (22/07/2019 - 16/11/2019) St Lucia Internal Course Profile
Semester 2, 2018 (23/07/2018 - 17/11/2018) St Lucia Internal Course Profile
Semester 2, 2017 (24/07/2017 - 18/11/2017) St Lucia Internal Course Profile
Semester 2, 2016 (25/07/2016 - 19/11/2016) St Lucia Internal Course Profile